In the electronics industry different semiconductor components have to be joined to each other. For each component a different method or process may be employed. The surface mounting method is sometimes used to connect one semiconductor component to another. Usually, one or both of the semiconductor components are provided with C4 (Controlled Collapse Chip Connection) pads, and then using reflow solder these semiconductor components are joined together. The semiconductor components or elements may be a chip or a substrate, such as for example, a multi-layer ceramic substrate.
A chip may be connected to a substrate using the effect of wetting and diffusion of a completely melted solder. Since it is necessary to melt the solder completely, segregation of the alloy occurs. This segregation often results in defects and residual stress that show up during the cooling stage of the solder.
The reflowed solder normally has a cast structure with low height and large circumferential area, i.e., low aspect ratio. The solder having a cast structure and low height sometimes has serious problems, such as, producing non-uniform strain, or solder being fractured by various kinds of stresses produced during accelerated life test. These fractures usually occur in a comparatively short period of time due to a variety of reasons, one of them being the metal fatigue of the solder.
Such a problem of solder interconnection has become more important with the increasing tendency towards miniaturization of electronic components or parts and an increase in mounting densities as in the case of LSI (Large Scale Integration) circuits.
The normal shape of a C4 connection is a truncated sphere with an aspect ratio, i.e., height to width ratio, of approximately 0.5. The flattened or barrel shape is not optimum from the standpoint of mechanical properties. Under induced stress, strain in the solder connection tends to be non-uniform and is concentrated in the reduced cross-sectional area near the terminations of the joint. And, since the strain is inversely proportional to the height, the strain is high due to the low aspect ratio. The shape of the solder mass is controlled by the solder surface tension forces acting on the molten ball of solder and the surface of the mounting component. Ways to overcome the surface tension forces of the molten solder have been explored, so as to increase the height (i.e., the aspect ratio) and reduce the strain concentration in the reduced sections near the termination. Such techniques have been shown to dramatically improve the fatigue life of solder joints since the fatigue life is inversely proportional to the square of the strain, i.e., one-half the strain gives four (4) times the fatigue life.
Another problem is the thermal expansion mismatch between a chip, such as a silicon chip, and a module or a substrate, such as an alumina substrate. Thermal expansion mismatch between the chip and the module produces mechanical stress in the joints because of the difference in coefficients of thermal expansion between the silicon of the circuit chip and the ceramic used for the module substrate. This thermal mismatch also generates shear strain on the C4 joint and thus reduces the life of the C4 joint. This problem has been partially solved by the use of ceramic substrates which match the thermal expansivity of the silicon chip, but still the dynamic shear strain or the thermal fatigue generated during switching on/off powering of the silicon circuitry cannot be eliminated and this results in fatigue failure of the C4 joint.
The above thermal fatigue problem, which differs from the mechanical fatigue in that fixed strain levels rather than fixed stress levels are exhibited, has long prevented the semiconductor industry from fabricating larger chips, or making high density C4 arrays with larger distance to neutral point. In short, the C4 fatigue problem has constrained the semiconductor industry from advancing to ultra-large-scale integration (ULSI).
Another method of extending the reliability of the C4 solder interconnect between a chip, such as a silicon chip and a substrate, such as an alumina substrate is to increase the chip "height", i.e., the distance from the chip mounting surface to the substrate.
In order to provide elongated solder connections between a semiconductor device and a supporting substrate, Lakritz et al. in U.S. Pat. No. 4,545,610, disclosed the use of solder extenders. On a supporting substrate a solder extender is formed, and a semiconductor device having solder mounds is invertedly placed over the substrate, such that solder extenders and the solder mounds have a direct surface to surface contact. This whole assembly is then heated to a temperature sufficient to melt the material of the solder extender and the solder mound, thus forming elongated hour-glass shaped solder connections between the device and the substrate.
Allen et al. in U.S. Pat. No. 4,664,309, taught that the life of a solder joint can be increased substantially by a relatively small increase in solder joint height, or that a reduction in solder joint diameter would also extend the life of a solder joint, and to this end they invented a mounting device to securely hold preforms of a joint-forming material in an aperture, such as a solder column.
Satoh et al. in U.S. Pat. No. 4,673,772, found another method of alleviating the kind of stresses produced due to the metal fatigue of the solder by having a low-melting point solder at the ends of a high-melting point solder that connects an assembly to a substrate, thereby getting high solder columns.
Recently, another technique has been presented to form stacked solder bumps. Solder bumps are stacked one on top of each other while a polyimide or ceramic film or sheet is used to support the solder bumps. See for example, European Patent Application Publication No. 229,850, or Matsui, N. et al., "VLSI Chip Interconnection Technology Using Stacked Solder Bumps", pp. 573-578, 1987 Proceedings of the 37th Electronic Components Conference, May 1987.
European Patent Application Publication No. 248,314, discloses the use of a mask, such as a photoresist, to act as a mold for the solder, and thereby producing large solder bump heights. Another method of producing large solder bump heights has been disclosed in European Patent Application Publication No. 248,566, where solder bumps on a bumped package and on the bumped substrate are heated and the contacting solder bumps melt together and coalesce to form an "elongated" solder joint.
There have been other proposals that have dealt with forming elongated solder bumps. One of the approaches was to stretch the solder by pulling chips from the substrate or module during solder reflow operation, thereby forming an "elongated" solder bump.
The elongated solder mass that is formed by the various aspects of this invention is simple and unique. The basic concept is to control the collapsing of the solder mass or bump by protecting it with an encapsulating material or layer. Additional solder mass or bumps that are formed over the first substantially encapsulated solder mass can also be protected by additional material or layer.
This invention also contemplates the formation of a barrier material or layer, that would reduce or eliminate intersolder diffusion. This barrier material or layer could be formed over the encapsulating material or layer, or the encapsulating material or layer itself could be the barrier layer or material.
The site that is used for the formation of the single or multilevel solder interconnection of this invention is normally an electronic component, such as a substrate or a chip. But the site for single or multi-level solder mass of this invention could be a ball limiting metallurgy layer or any electrical conductor.